1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a local data line pair and a global data line pair and a data read and write method thereof.
2. Description of the Related Art
A conventional semiconductor memory device includes a local data line pair and a global data line pair to increase the amount of data to be inputted and outputted.
In general, a semiconductor memory device pre-charges a local data line pair and a global data line pair before performing a data write operation and a data read operation, in order to increase data transmission speed. Also, the semiconductor memory device includes a sense amplifier in the global data line pair that amplifies and outputs data from the local data line pair to the global data line pair during a read operation.
FIG. 1 is a view illustrating a signal line arrangement of a memory cell array of a conventional semiconductor memory device.
In FIG. 1, WL denotes one respective word line of the memory cell array, and BL denote one respective bit line of the memory cell array.
In FIG. 1, each of memory cell array blocks BLK1˜n includes m sub memory cell arrays blocks blk1˜m. The word lines WL are arranged perpendicular to the memory cell array blocks BLK1˜n, and the bit lines BL are arranged in a transverse direction. Local data line pairs L/B11˜1k to L/Bn1˜nk are arranged in a perpendicular direction respectively between the memory cell array blocks BLK1˜n, and global data line pairs G/B1˜k are arranged in a transverse direction to connect to the local data line pairs L/B11˜n1 to L/B1k˜nk of the memory cell array blocks BLK1˜n, respectively.
In the semiconductor memory device of FIG. 1, the local data line pairs L/B11˜1k to L/Bn1˜nk are respectively divided to receive/output data from/to the m groups of the sub memory cell array blocks blk1˜m of the selected memory cell array block. And, the global data line pairs G/B1˜k receives/outputs data from/to the local data line pairs L/B11˜1k to L/Bn1˜nk.
The semiconductor memory device of FIG. 1 can simultaneously receive and output data.
FIG. 2 is a view illustrating the configuration of a semiconductor memory device of FIG. 1, which is connected between one local data line pair L and LB and one global data line pair G and GB.
In FIG. 2, the semiconductor memory device includes a memory cell array block BLK having memory cells MC, a column selecting gate 12, a local data line pre-charge circuit 14, a block selecting gate 16, a global data line pre-charge circuit 18, a sense amplifier 20, and a write driver 22.
Function of the components of FIG. 2 is explained below.
The memory cell array block BLK includes a plurality of memory cells MC connected between the word line WL and the bit line pair BL and BLB to write and read data. The column selecting gate 12 includes NMOS transistors N11 and N12 that transmit data between the bit line pair BL and BLB and the local data line pair L and LB in response to a column selecting signal CSL. The local data line pre-charge circuit 14 includes NMOS transistors N31 to N33 and pre-charges the local data line pair L and LB in response to a pre-charge control signal PRE. The block selecting gate 16 includes NMOS transistors N21 and N22 that transmit data between the local data line pair L and LB and the global data line pair G and GB in response to a block selecting signal BS. The global data line pre-charge circuit 18 includes PMOS transistors P11 to P13 that pre-charge the global data line pair G and GB in response to an inverted signal of the pre-charge control signal PRE. The sense amplifier 20 amplifies data of the global data line pair G and GB and outputs the data to the data line pair D and DB in response to a sense amplifier control signal IOSA during a read operation. The write driver 22 drives data of the data line pair D and DB and transmits the data to the global data line pair G and GB in response to a write control signal WE during a write operation.
The conventional semiconductor memory device of FIG. 2 pre-charges the local data line pair L and LB to the voltage level obtained by subtracting the threshold voltage Vth of the NMOS transistors N31 to N33 from the power voltage supplied to these NMOS transistors. Also, the memory device of FIG. 2 pre-charges the global data line pair G and GB to the power voltage level supplied to the PMOS transistors P11 to P13, during a pre-charge operation.
The conventional semiconductor memory device causes relatively high power consumption since the global data line pair G and GB is pre-charged to a power voltage level during a pre-charge operation. Also, the write speed is delayed when data having a logic “low” level is transmitted during a write operation due to the time it takes for the pre-charge level to fall to a logic “low” level.
For the foregoing reason, a method of designing the conventional semiconductor memory device so that the global data line pre-charge circuit 18 includes NMOS transistors like the local data line pre-charge circuit 14 is considered. In this case, there is an advantage of improving the write speed. However, when the global data line pair is pre-charged to the voltage level obtained by subtracting the threshold voltage Vth of the NMOS transistor from the power voltage, the voltage difference between the global data line pair is smaller during a read operation. As a result, the gain of the sense amplifier 20 is reduced, and it becomes impossible to amplify and output data of the global data line pair fast and efficiently, adversely affecting the read operation. Therefore, the conventional semiconductor memory device continues to be configured so that the local data line pair is comprised of NMOS transistors and the global data line pair is comprised of PMOS transistors, as shown in FIG. 2, and the novel improvement of the present invention accomplishes the goal of faster speed by another way, as described herein below.